1. Field of the Invention
This invention relates to semiconductor devices which are protected from damage resulting from electrostatic discharge (ESD). More specifically, this invention relates to semiconductor devices having selectively silicided ESD transistors.
2. Description of Related Art
Gates of metal-oxide semiconductor (MOS) transistors receive input signals and transfer output signals in the form of a voltage. The gate oxide can break down if the applied voltage exceeds certain levels. Such excess voltages are often the result of human-operator or mechanical handling operations. Triboelectricity is an electrical charge which evolves when two materials are rubbed together. Human operators can create this type of electricity by walking across a room or by removing an integrated circuit (IC) from its plastic package. Triboelectricity results in high voltage, which when applied to a semiconductor device in the form of electrostatic discharge (ESD) can cause breakdown of the gate oxide or overheating due to overcurrent. This breakdown can cause immediate or expedited destruction of transistors and other devices.
In order to combat problems associated with ESD events, manufacturers of MOS devices design protection devices that provide paths through which to discharge nodes rapidly. Protection devices frequently include a transistor positioned between the input buffer or output buffer pads of a device and the respective gates to which the pads are connected. This transistor is often referred to as an ESD transistor. During an ESD event, a typical ESD transistor enters snap-back, a low resistance regime in which large amounts of current are conducted.
Certain processing enhancements, such as siliciding source/drain regions, increase the performance of small-dimension devices, but often negate the benefits of ESD transistors. These silicided regions are often positioned near the drain junction of the ESD transistors. The drain junction is a major source of heat during an ESD event. The proximity of the silicide to the drain junction frequently causes the silicide to melt during an ESD event which further causes breakdown of the semiconductor device.
One attempt to reduce the exposure of the silicide to heat has been to increase the gate-to-contact spacing in ESD transistors. However, this increased length adds resistance that impedes the current discharging through the ESD transistor. Thus, current tends to flow through other transistors on the semiconductor device before discharging through the ESD transistor. Accordingly, the increased resistance can negate the benefits of the protection device.
Another problem associated with silicided source/drain regions in a protection device is known as the "ballasting" effect. Due to the greatly reduced resistance of silicided regions during an ESD event, the current discharging through the ESD transistor may collapse into a thin filament. This collapse can lead to increased heating and premature device failure.
Many of the difficulties associated with silicide can be solved by selectively blocking silicide formation on the source, drain and/or gate electrode of the ESD transistors in semiconductor devices. Techniques for selective blocking of silicide formation frequently require two or more independent N+ implants, formation of multiple oxide layers and/or three or more masking steps. Multiple implants, oxide layer formations and maskings add to the costs and difficulty of semiconductor manufacture. Accordingly, there is a need for a process of creating semiconductor devices while reducing the number of N+ implants, oxide layer formation, and masking steps.